This application claims the priority benefit of Taiwan application serial no. 89117012, filed Aug. 24, 2000.
1. Field of Invention
The present invention relates to an input/output buffer. More particularly, the present invention relates to a high-frequency low-voltage-variation transmission bus having an active pull-up device capable of saving the terminal resistors of a motherboard having a central processing unit socket.
2. Description of Related Art
To increase packing density of semiconductor devices and reduce power consumption, the best strategy is to lower the operating voltage of an integrated circuit. Furthermore, because of a constant increase in the operating frequency of a computer system, the transmission bus of most computer systems can operate at a very high frequency with very little voltage variation. For example, the gunning transmission logic (GTL+) bus is a typical high-frequency low-voltage-variation transmission bus.
FIG. 1 is a circuit diagram showing the basic connections of a conventional GTL+ bus that uses a GTL+ input/output buffer. As shown in FIG. 1, the GTL+ bus comprises a first GTL+ input/output buffer (IC1), a second CTL+ input/output buffer (IC2), a first transmission line 100, a second transmission line 102 and a terminal resistor rt2 (50xcexa9). One end of the terminal resistor rt2 is connected to a terminal voltage Vtt (1.5V) while the other end is connected to one end of the second transmission line 102. The other end of the second transmission line 102 is connected to one terminal of the first transmission line 100 and IC1. The other end of the first transmission line 100 is connected to IC2.
When IC2 serves as a transmitting terminal and IC1 serves as a receiving terminal, the terminal IC1 receives very little ring back interference because IC1 is relatively close to the terminal resistor rt2. On the contrary, if IC1 is used as a transmitting terminal while IC2 is used as a receiving terminal, waveform received may be distorted due to a ring back effect resulting from a lack of terminal resistor nearby. Ring back effect can be reduced by adding a 50xcexa9 resistor connected a voltage Vtt inside IC2 or adding a 50xcexa9 resistor to a printed circuit board outside IC2 (a resistor rt1 on the transmission line 104).
However, due to the presence of two terminal resistors rt1 and rt2, power consumption increases considerably. In addition, forming another 50 resistors on a printed circuit board outside each IC2 increases the area requirement of the printed circuit board as well as production cost.
FIG. 2 is a circuit diagram showing the connections from a Pentium II central processing unit (CPU) to a conventional Pentium II motherboard through a dedicated slot. Because the Pentium II CPU uses a single edge contact cartridge (SECC) having a printed circuit board (PCB) 203 therein, the Pentium II CPU, cache memory and terminal resistor rt2 are integrated together on the PCB 203. Since the PCB 203 has considerable space, putting the terminal resistor rt2 on the PCB 203 results in no routing problem for the Pentium II motherboard. The input/output buffer 2011 inside the Pentium II chipset 201 has a built-in terminal resistor rt1 connected to a terminal voltage Vtt. A signal sent from the input/output buffer 2011 is forwarded to the printed circuit board 203 after passing through the transmission line 202. Similarly, the input/output buffer 2032 inside the PCB 203 of the SECC is connected via a transmission line 2031 to another resistor rt2 and then to a terminal voltage Vtt. With such transmission routing, each end has a terminal resistor capable of reducing ring back effect.
FIG. 3 is a schematic diagram showing a PCB routing layout on a motherboard close to the CPU socket. As shown in FIG. 3, a pin grid array (PGA) central processing unit (not shown) is connected to a chipset 301 by plugging into a CPU socket 302. Unlike the SECC PCB of a Pentium II CPU, a PGA CPU does not have a SECC PCB. Hence, the PGA CPU must attach a terminal resistor rt2 on the motherboard 300 close to the CPU socket 302. Because a PGA socket usually has a large number of pins, there is limited space between the socket pins. Hence, difficulties in routing on the motherboard 300 are often encountered when attempts are made to locate a terminal resistor rt2 at a position close to the CPU socket 302. For example, after the chipset 301 connects a signal line to the CPU socket 302, the connecting line has to re-route out of the socket 302 on the motherboard 300 to connect with terminal resistors rt2. Hence, wiring between two socket pins has to double, resulting in serious routing problems.
FIG. 4 is a circuit diagram showing the resistor regulator of a conventional input/output buffer. As shown in FIG. 4, the resistor regulator 400 includes an input/output buffer 409, PMOS transistors 401, 402, 403, NMOS transistors 405, 406, 407, an output transistor 404 and a resistor R1. Through external signals PEN, {overscore (ZI+OEN)} and {overscore ((A*OEN))}, the equivalent resistance between the source and drain terminal of the output transistor 404 and resistor R1 are serially connected to produce a variable resistance in the range of about 100-200xcexa9. Hence, ring back effect on the bus is minimized. Yet, power is still consumed by the terminal resistor at the other end of the bus. Furthermore, the drain terminals of the PMOS transistors 401, 402403 inside the conventional resistor regulator 400 are connected to a terminal voltage Vtt. Consequently, the number of terminal voltage (Vtt) balls supplied by the chipset (in BGA package) is insufficient, leading to a large inductance on the Vtt balls. When the output transistor 404 is switched xe2x80x98ONxe2x80x99, the terminal voltage Vtt drops to about 0.9V. A terminal voltage of around 0.9V is very close to the threshold voltage Vth of the output transistor 404. Therefore, the variable resistance resulting from the serial connection of the equivalent resistance between the source and the drain terminal of the output transistor 404 and the resistor R1 may change from about 100-200xcexa9 to about a thousand xcexa9. Thus, not only the power consumption of the terminal resistor on the motherboard is not reduced, but the ring back effect is not improved either.
Accordingly, one object of the present invention is to provide a control circuit capable of saving terminal resistors on a motherboard and suitable for operating on a high-frequency low-voltage-variation transmission bus such as a GTL+ bus. The invention utilizes a field effect transistor to locate a terminal resistor between an input/output buffer and a first voltage source when a pull-up enable signal is asserted. Hence, there is no need to use a terminal resistor at either end of the bus when external resistor rt2 is eliminated.
A second object of the invention is to provide a chipset capable of saving terminal resistors on a motherboard and suitable for operating on a high-frequency low-voltage-variation transmission bus such as a GTL+ bus. The chipset is capable of providing an output resistance of about 45-60xcexa9 to replace an external terminal resistor rt2. Therefore, motherboard routing is simplified and the area requirement of the motherboard is reduced.
A third object of the invention is provide a method capable of saving terminal resistors on a motherboard and suitable for operating on a high-frequency low-voltage-variation transmission bus such as a GTL+ bus. By activating a pull-up enable signal, a control circuit outputs a resistance of about 45-60xcexa9 to replace an external terminal resistor rt2. Therefore, motherboard routing is simplified and the area requirement of the motherboard is reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a control circuit to be used inside an input/output buffer capable of saving terminal resistors on a motherboard. The input/output buffer is suitable for operating on a high-frequency low-voltage-variation transmission bus. The input/output buffer has an input/output pad. The control circuit includes a first field effect transistor, a second field effect transistor and a third field effect transistor. The gate terminal of the first field effect transistor is connected to a pull-up enable signal line and a first source/drain terminal of the first field effect transistor is connected to a first voltage source. The gate terminal of the second field effect transistor is connected to the pull-up enable signal line. A first source/drain terminal of the second field effect transistor is connected to a second source/drain terminal of the first field effect transistor. A second source/drain terminal of the second field effect transistor is connected to a ground. The gate terminal of the third field effect transistor is connected to the second source/drain terminal of the first field effect transistor. A first source/drain terminal of the third field effect transistor is connected to a second voltage source. A second source/drain terminal of the third field effect transistor is connected to the input/output pad. When the pull-up enable signal is activated, the second field effect transistor is cut off while the first field transistor is turned on. Hence, an equivalent resistance is set up between the source and the drain terminal of the third field effect transistor in parallel between the input/output pad and the second voltage source. An equivalent resistance of about 45-60xcexa9 is set to replace another terminal resistor rt2 at the other end of the external bus. Ultimately, motherboard routing is simplified. When the pull-up enable signal is disabled, the second field effect transistor is turned on while the first and the third field effect transistors are cut off. Consequently, an infinite resistance is set up between the source and the drain terminal of the third field effect transistor in parallel between the input/output pad and the second voltage source. Hence, the motherboard can now use the terminal resistor rt2 at the other end of the bus.
This invention also provides a chipset capable of savingterminal resistors on a motherboard and suitable for operating on a high-frequency low-voltage-variation transmission bus. The chipset includes an input/output pad for receiving a signal and a control circuit for outputting a terminal resistor. The control circuit comprises a first field effect transistor, a second field effect transistor and a third field effect transistor. The gate terminal of the first field effect transistor is connected to a pull-up enable signal line and a first source/drain terminal of the first field effect transistor is connected to a first voltage source. The gate terminal of the second field effect transistor is connected to the pull-up enable signal line. A first source/drain terminal of the second field effect transistor is connected to a second source/drain terminal of the first field effect transistor. A second source/drain terminal of the second field effect transistor is connected to a ground. The gate terminal of the third field effect transistor is connected to the second source/drain terminal of the first field effect transistor. A first source/drain terminal of the third field effect transistor is connected to a second voltage source. A second source/drain terminal of the third field effect transistor is connected to the input/output pad. When the pull-up enable signal is activated, the second field effect transistor is cut off while the first field transistor is turned on. Hence, an equivalent resistance is set up between the source and the drain terminal of the third field effect transistor in parallel between the input/output pad and the second voltage source. The equivalent resistance thus set up replaces another terminal resistor rt2 at the other end of the external bus. Ultimately, motherboard routing is simplified and area requirement of the motherboard is reduced. When the pull-up enable signal is at a low potential, the second field effect transistor is turned on while the first and the third field effect transistor are cut off. Consequently, an infinite equivalent resistance is set up between the source and the drain terminal of the third field effect transistor in parallel between the input/output pad and the second voltage source. The infinite equivalent resistance between the input/output pad and the second voltage source has no effect on the terminal resistor rt2 at the other end of the bus. Hence, the motherboard can now use the terminal resistor rt2 at the other end of the external bus.
This invention also provides a method capable of saving terminal resistors on a motherboard and suitable for operating on a high-frequency low-voltage-variation transmission bus. The method includes providing a pull-up enable signal, a first field effect transistor, a second field effect transistor and a third field effect transistor. The gate terminal of the first field effect transistor is connected to the pull-up enable signal line. A first source/drain terminal of the first field effect transistor is connected to a first voltage source. The gate terminal of the second field effect transistor is connected to the pull-up enable signal line. A first source/drain terminal of the second field effect transistor is connected to a second source/drain terminal of the first field effect transistor. A second source/drain terminal of the second field effect transistor is connected to a ground. The gate terminal of the third field effect transistor is connected to the second source drain terminal of the first field effect transistor. A first source/drain terminal of the third field effect transistor is connected to a second voltage source. A second source/drain terminal of the third field effect transistor is connected to the input/output pad.
When the pull-up enable signal is activated, the second field effect transistor is cut off while the first field transistor is turned on. Hence, an equivalent resistance of about 45-60xcexa9 is set up between the source and the drain terminal of the third field effect transistor in parallel between the input/output pad and the second voltage source. Thus, the terminal resistor rt2 at the other end of the bus on the motherboard can be cut out. When the pull-up enable signal is disabled, the second field effect transistor is turned on while the first field effect transistor and the third field effect transistor are cut off. Consequently, an infinite resistance is set up between the source and the drain terminal of the third field effect transistor in parallel between the input/output pad and the second voltage source. Hence, the motherboard can now use the terminal resistor rt2 at the other end of the bus.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.